# Miller effect when switching MOS tube!

01

Basic principles of Miller platform formation

The MOSFET gate driving process can be simply understood as the charging and discharging process of the driving source to the MOSFET’s input capacitance (mainly the gate-source capacitance Cgs); when Cgs reaches the threshold voltage, the MOSFET enters the on state; when the MOSFET is turned on Later, Vds began to fall, and Id started to rise. At this time, the MOSFET entered the saturation region. However, due to the Miller effect, Vgs will continue to rise for a period of time, at this time Id has reached the maximum, and Vds continues to decline until the Miller capacitor. When fully charged, Vgs rises to the value of the driving voltage again. At this time, the MOSFET enters the resistance area. At this time, Vds is completely lowered and the turn-on is completed.

Because the Miller capacitance prevents the rise of Vgs and thus the decline of Vds, this will increase the loss time. (Vgs rises, the on-resistance decreases, and Vds decreases)

The Miller effect is notorious in MOS driving. He is the Miller effect caused by the Miller capacitance of the MOS tube. During the turn-on of the MOS tube, the GS voltage has a stable value after the GS voltage rises to a certain voltage value. The voltage starts to rise again until it is fully turned on. Why is there a stable value? Because, before the MOS is turned on, the D-pole voltage is greater than the G-pole voltage. The electric energy stored in the MOS parasitic capacitor Cgd needs to be injected into the G-pole to neutralize the charge when it is turned on, because the G-pole voltage is greater than the D-pole after the MOS is fully turned on. Voltage. The Miller effect will seriously increase the turn-on loss of the MOS. (The MOS tube cannot enter the switching state quickly)

So there is a so-called totem driver! !! When MOS is selected, the smaller the Cgd, the smaller the turn-on loss. The Miller effect cannot completely disappear.

The Miller platform in the MOSFET is actually a typical sign that the MOSFET is in the “amplification zone”.

By measuring the GS voltage with an oscilloscope, you can see that there is a platform or pit during the voltage rise. This is the Miller platform.

02

Detailed process of Miller platform formation

The Miller effect means that the Miller platform will be generated during the pass of the MOS tube. The principle is as follows.

Theoretically, the driver circuit can add Miller capacitor between G and S to eliminate the Miller effect. But at this time the switch time will be long. Generally recommended value plus 0.1Ciess capacitor value is good.

The flat part of the thick black line in the picture below is the Miller platform.

This graph of decoupling coefficient is at the first turning point: Vds starts to conduct. The change of Vds forms a differential through the internal resistance of Cgd and the driving source. Because Vds decreases approximately linearly, linear differentiation is a constant, resulting in a plateau at Vgs.

The Miller platform is caused by the capacitance across the g d of the mos, that is, Crss in the mos datasheet.

This process is to charge Cgd, so Vgs changes little. When Cgd is charged to Vgs level, Vgs starts to continue to rise.

When Cgd was first turned on, it was quickly discharged through mos and then reversely charged by the driving voltage, sharing the driving current, making the voltage rise on Cgs slower and appearing as a platform.

0 ~ t1: Vgs from 0 to Vth. Mosfet is not connected.

t1 ~ t2: Vgs from Vth to Va. Id

t2 ~ t3: Vds drops. Causes the current to continue to pass through Cgd. The higher the Vdd, the longer it takes.

Ig is the drive current.

It starts to fall faster. When Vdg is close to zero, Cgd increases. Until Vdg becomes negative, Cgd increases to the maximum. The decline becomes slower.

t3 ~ t4: Mosfet is fully turned on and runs in the resistance area. Vgs continues to rise to Vgg.

In the late stage of the platform, VGS continued to increase, and IDS changed little because MOS was saturated. . . However, from the figure of the landlord, this platform still has a length of length.

During this platform, it can be considered that MOS is in the magnification period.

Before the previous inflection point: the MOS deadline, at which point Cgs is charged and Vgs is approaching Vth.

At the previous inflection point: MOS officially entered the amplification period

At the next inflection point: MOS officially exits the amplification period and begins to enter the saturation period.

When a voltage V with a slope of dt is applied to the capacitor C (such as the output voltage of the driver), the current in the capacitor will increase:

I = C × dV / dt (1)

Therefore, when a voltage is applied to the MOSFET, an input current Igate = I1 + I2 is generated, as shown in the figure below.

Using equation (1) on the right voltage node, we get:

I1 = Cgd × d (Vgs-Vds) / dt = Cgd × (dVgs / dt-dVds / dt) (2)

I2 = Cgs × d (Vgs / dt) (3)

If the gate-source voltage Vgs is applied to the MOSFET, its drain-source voltage Vds will drop (even if it drops non-linearly). Therefore, the negative gain connecting these two voltages can be defined as:

Av =-Vds / Vgs (4)

Substituting equation (4) into equation (2), we get:

I1 = Cgd × （1 + Av） dVgs / dt (5)

During the transition (on or off), the total equivalent capacitance Ceq of the gate-source is:

Igate = I1 + I2 = (Cgd × (1 + Av) + Cgs) × dVgs / dt = Ceq × dVgs / dt (6)

The term (1 + Av) in the formula is called the Miller effect, and it describes the capacitive feedback between the output and input in an electronic device. When the gate-drain voltage approaches zero, the Miller effect will occur.

The most powerful stage of Cds shunting is in the magnified area. Why? Because Vd changes most drastically at this stage. The platform was formed at exactly this stage. You can think: the gate current Igate is completely absorbed by Cds, and no current flows to Cgs.

Note the representation in the data sheet

Ciss=Cgs+Cgd

Coss=Cds+Cgd

Crss=Cgd